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--- projects:archevo:isa [2021/04/20 02:33] – Owen Mellema
+++ projects:archevo:isa [2021/04/21 00:03] (current) – [ISAs in ArchEvo] Owen Mellema
@@ Line 1: / Line 1: @@
-====== Evolvable ISA ======
+====== ISAs in ArchEvo ======
 ===== What is an ISA? =====
-An //ISA//, short for Instruction Set Architecture, is the convention that allows programmers to talk to computers. The programmer can write a string of bits, give it to a CPU, and the CPU will do something. It is the most basic form of programming language. In fact, all programming languages are eventually turned into a series of bits based off of the ISA. 9The series of bits is sometimes called Assembly Language, but that isn't important here.)
+An //ISA//, short for Instruction Set Architecture, is the convention that allows programmers to talk to computers. The programmer can write a string of bits, give it to a CPU, and the CPU will do something. It is the most basic form of programming language. In fact, all programming languages are eventually turned into a series of bits based off of the ISA. (The series of bits is sometimes called Assembly Language, but that isn't important here.)
 ===== Brittleness =====
-ISAs that are practically used are generally //brittle//. This means that if a random bit flips in an instruction, the results will likely be catastrophic (for the execution of the program, that is). Although this isn't a purposeful choice on the parts of the designers of these ISAs, it isn't necessarily a bad thing. Consider, for example, an ATM. if a "cosmic ray" hits the CPU, and an instruction has a bit flip, we (or, at least, the bankers) don't want it to continue running as if nothing had happened, as this could lead to a loss of money. Instead, they would rather the program fail, and just be rebooted.
+ISAs that are practically used are generally //brittle//. This means that if a random bit flips in an instruction, the results will likely be catastrophic (for the execution of the program, that is). Although this isn't a purposeful choice on the parts of the designers of these ISAs, it isn't necessarily a bad thing. Consider, for example, an ATM. If a "cosmic ray" hits the CPU, and an instruction has a bit flip, we (or, at least, the bankers) don't want it to continue running as if nothing had happened, as this could lead to a loss of money. Instead, they would rather the program fail, and just be rebooted.
 Brittleness is caused by two main factors.
@@ Line 54: / Line 54: @@
 In ArchEvo, I want cells to be able to look into the registers of adjacent cells, but not to change the value of these registers. That is, cells have read/write privileges on their own registers, but only read privileges on their own. So what happens when a cell attempts to write to a register it does not have access to?
+To motivate this example, I will use the ASIA instruction set. In this example, REG_A is an internal register referenced by code 0b0011, and I_REG_A is an external register referenced by code 0b1011. Finally, MOVE_REGISTER is 100. If we put these together, we can make an instruction that seems to move REG_A into I_REG_A, overwriting the contents of that register.
+<code>
+MOVE_REGISTER REG_A I_REG_A
+           0011  1011
+</code>
+All seems lost, until the magical Ghost Bit appears! 👻 The Ghost Bit changes MOVE_REGISTER to UNASSIGNED, which tells the cell to pause.
+<code>
+   UNASSIGNED REG_A I_REG_A
+[1]100        0011  1011
+</code>
+So where did the Ghost Bit come from? Well, consider that whether or not a register is writable is true or false, so it can be expressed as a bit. This is the Ghost Bit. So, when the result register is writable, the ghost bit is 0, but when it is not writable, the ghost bit is 1. The operation that would have caused a fault is swapped out for an operation that cannot cause a fault.
 The Ghost Bit system makes ISAs faultless by making it impossible for a fault to arise. It does this by interpreting any instruction that //could// lead to a fault as an instruction that will not cause a fault.
+===== Other ISA features in ArchEvo =====
+==== IPLOC ====
+In order for cells to be able to observe other cells' registers, they must be able to manipulate an offset to that cell. We can limit this to the eight adjacent squares around a cell to make this easier.
+The naïve approach would be to store each offset as a number in a register. There are two problems with this. Firstly, interpreting the register as an unsigned int, the possible range for observation becomes a square of size 256 around the cell. This is not what we want. Secondly, this requires two registers, which is not ideal.
+The IPLOC (**I**nspection **P**ointer **LOC**ation) convention circumvents this by encoding each of the eight offsets as a bit in a single register. The actual offset is the most significant bit in the register.
+<code>
+xxxxxxx => ( 1,  1)
+xxxxxx => ( 0,  1)
+xxxxx => (-1,  1)
+xxxx => ( 1,  0)
+xxx => (-1,  0)
+xx => ( 1, -1)
+0000001x => ( 0, -1)
+00000001 => (-1, -1)
+00000000 => ( 0,  0)
+</code>
+===== ISAs in ArchEvo =====
+The following is a list of the ISAs in ArchEvo:
+  * [[projects:archevo:asia|ASIA]]