Differences

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--- projects:archevo:asia [2021/04/20 17:43] – Owen Mellema
+++ projects:archevo:asia [2021/04/21 14:55] (current) – [Registers] Owen Mellema
@@ Line 2: / Line 2: @@
 **ASIA**, short for **A**rchEvo **S**tandard **I**nstruction set **A**rchitecture, is an [[projects:archevo:ISA]] in ArchEvo. It was the original ISA that was created for ArchEvo. It was the only ISA supported in ArchEvo Classic, and is currently the only available ISA in ArchEvo Pangea, although research is being done on it's successor.
-===== Operations =====
+===== Instructions =====
-ASIA uses the [[https://wiki.owenmellema.com/projects:archevo:isa#ghost_bits|Ghost Bit]] system, so while there are only three bits of opcode, there are 16 possible instructions.
 ASIA instructions are eleven bits long.
@@ Line 13: / Line 12: @@
 </code>
-^ GB ^ Opcode ^ Command            ^ Description                               ^
+===== Operations =====
-| 0  | 000    | INC <reg1>         | Increments reg1                           |
+ASIA uses the [[projects:archevo:isa#ghost_bits|Ghost Bit]] system, so while there are only three bits of opcode, there are 16 possible instructions.
-| 0  | 001    | DEC <reg1>         | Decrements reg1                           |
-| 0  | 010    | SLL <reg1>         | Shifts reg1 left                          |
+^ GB ^ Opcode ^ Command            ^ Description                               ^ Action Type            ^
-| 0  | 011    | SRL <reg1>         | Shifts reg1 right                         |
+| 0  | 000    | INC <reg1>         | Increments reg1                           | RegisterUpdate         |
-| 0  | 100    | MOV <reg1> <reg2>  | Move value of reg2 to reg1                |
+| 0  | 001    | DEC <reg1>         | Decrements reg1                           | RegisterUpdate         |
-| 0  | 101    | SLT <reg1> <reg2>  | Set reg1 to 0xFF if reg1 < reg2 else 0x00 |
+| 0  | 010    | SLL <reg1>         | Shifts reg1 left                          | RegisterUpdate         |
-| 0  | 110    | SGT <reg1> <reg2>  | Set reg1 to 0xFF if reg1 > reg2 else 0x00 |
+| 0  | 011    | SRL <reg1>         | Shifts reg1 right                         | RegisterUpdate         |
-| 0  | 111    | SET <reg1> <reg2>  | Set reg1 to 0xFF if reg1 = reg2 else 0x00 |
+| 0  | 100    | MOV <reg1> <reg2>  | Move value of reg2 to reg1                | RegisterUpdate         |
-| 1  | 000    | REP                | Reproduce at IPLOC                        |
+| 0  | 101    | SLT <reg1> <reg2>  | Set reg1 to 0xFF if reg1 < reg2 else 0x00 | RegisterUpdate         |
-| 1  | 001    | JMP                | Jump                                      |
+| 0  | 110    | SGT <reg1> <reg2>  | Set reg1 to 0xFF if reg1 > reg2 else 0x00 | RegisterUpdate         |
-| 1  | 010    | JMC <reg2>         | Jump if reg2 = 0xFF                       |
+| 0  | 111    | SET <reg1> <reg2>  | Set reg1 to 0xFF if reg1 = reg2 else 0x00 | RegisterUpdate         |
-| 1  | 011    | MOV                | Move cell in direction of IPLOC           |
+| 1  | 000    | REP                | Reproduce at IPLOC                        | Reproduce              |
-| 1  | 100    | NON                | //UNASSIGNED//                            |
+| 1  | 001    | JMP                | Jump*                                     | MoveInstructionPointer |
-| 1  | 101    | NPA                | NOP A, part of jump templating            |
+| 1  | 010    | JMC <reg2>         | Jump* if reg2 = 0xFF                      | MoveInstructionPointer |
-| 1  | 110    | NPB                | NOP B, part of jump templating            |
+| 1  | 011    | MOV                | Move cell in direction of IPLOC           | Move                   |
-| 1  | 111    | ATK                | Attack cell at IPLOC                      |
+| 1  | 100    | NON                | //UNASSIGNED//                            | DoNothing              |
+| 1  | 101    | NPA                | NOP A, part of jump templating            | DoNothing              |
+| 1  | 110    | NPB                | NOP B, part of jump templating            | DoNothing              |
+| 1  | 111    | ATK                | Attack cell at IPLOC                      | Attack                 |
+*Jumping uses [[ projects:archevo:isa#template_jumps | Template Jumps ]]
+===== Registers =====
+There are two types of registers - virtual and physical. Physical registers are the eight registers that actually exist in the Cell. Virtual registers are registers that exist outside of the cell, at the [[projects:archevo:isa#iploc | IPLOC]]. (( The IPLOC is register 7 ))
+The first bit of the register pointer represents whether or not it is virtual. If the register is physical, the first bit will be 0. If virtual, it will be 1. The last three bits are the register number.
+We have R/W access to all physical registers except 0b0000, which is energy.