Table of Contents

ASIA

ASIA, short for ArchEvo Standard Instruction set Architecture, is an ISA in ArchEvo. It was the original ISA that was created for ArchEvo. It was the only ISA supported in ArchEvo Classic, and is currently the only available ISA in ArchEvo Pangea, although research is being done on it's successor.

Instructions

ASIA instructions are eleven bits long.

OOO22221111
O - Opcode
1 - Register 1
2 - Register 2

Operations

ASIA uses the Ghost Bit system, so while there are only three bits of opcode, there are 16 possible instructions.

GB Opcode Command Description Action Type
0 000 INC <reg1> Increments reg1 RegisterUpdate
0 001 DEC <reg1> Decrements reg1 RegisterUpdate
0 010 SLL <reg1> Shifts reg1 left RegisterUpdate
0 011 SRL <reg1> Shifts reg1 right RegisterUpdate
0 100 MOV <reg1> <reg2> Move value of reg2 to reg1 RegisterUpdate
0 101 SLT <reg1> <reg2> Set reg1 to 0xFF if reg1 < reg2 else 0x00 RegisterUpdate
0 110 SGT <reg1> <reg2> Set reg1 to 0xFF if reg1 > reg2 else 0x00 RegisterUpdate
0 111 SET <reg1> <reg2> Set reg1 to 0xFF if reg1 = reg2 else 0x00 RegisterUpdate
1 000 REP Reproduce at IPLOC Reproduce
1 001 JMP Jump* MoveInstructionPointer
1 010 JMC <reg2> Jump* if reg2 = 0xFF MoveInstructionPointer
1 011 MOV Move cell in direction of IPLOC Move
1 100 NON UNASSIGNED DoNothing
1 101 NPA NOP A, part of jump templating DoNothing
1 110 NPB NOP B, part of jump templating DoNothing
1 111 ATK Attack cell at IPLOC Attack

*Jumping uses Template Jumps

Registers

There are two types of registers - virtual and physical. Physical registers are the eight registers that actually exist in the Cell. Virtual registers are registers that exist outside of the cell, at the IPLOC. 1)

The first bit of the register pointer represents whether or not it is virtual. If the register is physical, the first bit will be 0. If virtual, it will be 1. The last three bits are the register number.

We have R/W access to all physical registers except 0b0000, which is energy.

1)
The IPLOC is register 7